Company Name: Excellent Integrated System LIMITED

Contact Person : John

Email/Msn     :John(at)eis-ic.com

Tel: 00852-30777742

Add.: RM 906, WORKINGBERG COMM BLDG, 41-47 MARBLE RD, HONGKONG

Excellent Integrated System LIMITED (EIS LIMITED), Established in 1991, is a professional independent stocking distributor of electronic components and specialize in buying the EXCESS STOCK from the original equipment manufacturers (OEMs), Contract equipment manufacturers (CEMs), and many other factories. EIS has gained good experiences in Excess Inventory Management through its development over 20 years and has become the reliable partner for the domestic and foreign OEM manufacturers. If any inquiry and question,please email us: John(at)eis-ic.com.

Description as follow:

The IR2104S is a high voltage, high speed power MOSFET and IGBT driver with dependent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction.

Parametrics

Absolute maximum ratings: (1)High side floating absolute voltage: -0.3 V min and 625 max; (2)High side floating supply offset voltage: VB - 25 V min and VB + 0.3 V max; (3)High side floating output voltage: VS - 0.3 to VB + 0.3 V; (4)Low side and logic fixed supply voltage -0.3 to 25 V; (5)Low side output voltage -0.3 VCC + 0.3 V; (6)Logic input voltage (IN & SD) -0.3 VCC + 0.3 V; (7)Allowable offset supply voltage transient: 50 V/ns; (8)Package power dissipation @ TA ≤ +25℃: (8 lead PDIP): 1.0W, (8 lead SOIC): 0.625W; (9)Thermal resistance, junction to ambient: (8 lead PDIP): 125150℃/W, (8 lead SOIC): 200150℃/W; (10)Junction temperature: 150℃; (11)Storage temperature: -55 to 150℃; (12)Lead temperature (soldering, 10 seconds): 300℃.

Features

Features: (1)Floating channel designed for bootstrap operation Fully operational to +600V Tolerant to negative transient voltage; (2)dV/dt immune; (3)Gate drive supply range from 10 to 20V; (4)Undervoltage lockout; (5)3.3V, 5V and 15V input logic compatible; (6)Cross-conduction prevention logic; (7)Internally set deadtime; (8)High side output in phase with input; (9)Shut down input turns off both channels; (10)Matched propagation delay for both channels; (11)Also available LEAD-FREE.

Diagrams