Company Name: Excellent Integrated System LIMITED

Contact Person : John

Email/Msn    :John(at)eis-ic.com

Tel          : 00852-30777742

Add.: RM 906, WORKINGBERG COMM BLDG, 41-47 MARBLE RD, HONGKONG

Excellent Integrated System LIMITED (EIS LIMITED), Established in 1991, is a professional independent stocking distributor of electronic components and specialize in buying the EXCESS STOCK from the original equipment manufacturers (OEMs), Contract equipment manufacturers (CEMs), and many other factories. EIS has gained good experiences in Excess Inventory Management through its development over 20 years and has become the reliable partner for the domestic and foreign OEM manufacturers. If any inquiry and question,please email us: john(at)eis-ic.com.

Description as follow:

The DS90LV110TMTC is a 1 to 10 data/clock distributor utilizing LVDS(Low Voltage Differential Signaling) technology for low power, high speed operation. The DS90LV110TMTC can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz. The DS90LV110TMTC accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.

Parametrics

DS90LV110TMTC absolute maximum ratings: (1)Supply Voltage (VDD-VSS):-0.3V to +4V; (2)LVCMOS/LVTTL Input Voltage(EN):-0.3V to (VCC + 0.3V); (3)LVDS Receiver Input Voltage(IN+, IN-):-0.3V to +4V; (4)LVDS Driver Output Voltage(OUT+, OUT-):-0.3V to +4V; (5)Junction Temperature:+150℃; (6)Storage Temperature Range:-65℃ to +150℃; (7)Lead Temperature(Soldering, 4 sec.):+260℃.

Features

DS90LV110TMTC features: (1)Low jitter 800 Mbps fully differential data path; (2)145 ps (typ) of pk-pk jitter with PRBS = 223-1 data pattern at 800 Mbps; (3)Single +3.3 V Supply; (4)Less than 413 mW (typ) total power dissipation; (5)Balanced output impedance; (6)Output channel-to-channel skew is 35ps (typ); (7)Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load; (8)LVDS receiver inputs accept LVPECL signals; (9)Fast propagation delay of 2.8 ns (typ); (10)Receiver input threshold < ±100 mV; (11)28 lead TSSOP package; (12)Conforms to ANSI/TIA/EIA-644 LVDS standard.

Diagrams