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Description as follow:

The MPC5200CVR400B is a SDRAM/DDR Memory Controller. It integrates a high performance MPC603e series e300 core with a rich set of peripheral functions focused on communications and systems integration. The e300 core design is based on the PowerPC core architecture. MPC5200CVR400B incorporates an innovative BestComm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded e300 core.

Parametrics

MPC5200CVR400B absolute maximum ratings: (1)Supply voltage - e300 core and peripheral logic: –0.3 to 1.8 V; (2)Supply voltage - I/O buffers: –0.3 to 3.6 V; (3)Supply voltage - System APLL: –0.3 to 2.1 V; (4)Supply voltage - e300 APLL: –0.3 to 2.1 V; (5)Input voltage (VDD_IO): –0.3 to VDD_IO + 0.3 V; (6)Input voltage (VDD_MEM_IO): –0.3 to VDD_MEM_IO + 0.3 V; (7)Input voltage overshoot: 1.0 V; (8)Input voltage undershoot: 1.0 V; (9)Storage temperature range: –55 to 150 ℃.

Features

MPC5200CVR400B features: (1)MPC603e series e300 core: Superscalar architecture, 760 MIPS at 400 MHz (-40 to +85 ℃), 16 k Instruction cache, 16 k Data cache, Double precision FPU; (2)SDRAM / DDR Memory Interface: up to 133-MHz operation, SDRAM and DDR SDRAM support, 256-MByte addressing range per CS, two CS available; (3)Flexible multi-function External Bus Interface: Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices, 8 programmable Chip Selects, Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address.

Diagrams